programmable logic device

The development course 、 exploitation flow 、 exploitation environment and hardware description language of programmable logic device are discussed in detail too.

介绍了可编程逻辑器件的发展历程、开发流程、开发环境、硬件描述语言等内容。

The programmable logic device of FPGA is a core controller unit of the design and it is composed of three modules: the process control course module, parameters setting and calling module and communication module.

该设计以可编程逻辑器件为核心控制部件，它由工序控制流程模块、参数设置及调用模块和通讯模块三个模块组成；

Hardware description language VHDL is very powerful for the application design of programmable logic device.

硬件描述语言VHDL非常适用于可编程逻辑器件的应用设计。

Design of Time-controller with Programmable Logic Device

应用可编程逻辑器件实现时间控制器芯片的设计

Using The ispLSI Programmable Logic Device To Realize Image Synthesis

一种用ispLSI可编程逻辑器件实现图象合成的方法

Technology on configurable system-on-chip FPGA ( Field Programmable Gate Array) is a kind of programmable logic device.

可配置片上系统技术FPGA属于可编程逻辑器件，芯片内部以阵列状排列各种可配置逻辑模块。

In order to improve the coding speed for angle encoder, using hardware describing language based Complex Programmable Logic Device ( CPLD), a new coding method was designed for matrix axile angle encoder.

为提高矩阵式编码器的译码速度，提高可靠性，设计一种新型译码方法。程序软、硬件结构。

This paper introduces a method to design frequency measuring circuit with the function of automatic range change by employing AHDL technology and describes in detail its working principle, designing thought and ways to realize by using Complex Programmable Logic Device ( CPLD).

介绍了应用AHDL技术设计带有自动量程切换功能的频率测量电路的方法。详细叙述了其工作原理和设计思想，并用复杂可编程器件CPLD予以实现。

Through the programmable logic device ( PLD), the first-in first-out ( FIFO)'s four precise clock and write enabling signals can be achieved, thus the accuracy of the whole system and flexibility of the time delay are increased.

通过PLD能够得到FIFO4路精确的时钟和读写使能信号，从而提高了整个系统的工作时钟精确度和延时的灵活性。

Study on the technique of the time domain equalizer in OFDM systems First, this paper generally introduces the development of Programmable Logic Device ( PLD) and the characteristic of FPGA.

正交频分复用调制中的一种时域均衡器本论文内容安排如下：第一章介绍了PLD（可编程逻辑器件）和OFDM（正交频分复用）技术的发展历史。

Complex Programmable Logic Device ( CPLD) is one of Application Specific Integrated Circuit ( ASIC) that has been widely used, especially adapt to design digital system.

复杂可编程逻辑器件（CPLD）是目前应用最为广泛的可编程专用集成电路（ASIC）之一，特别适合于数字系统的设计和开发。

Through the research of data-acquiring technique, a suit of programmable telemetry signal acquisition and encoding system based on DSP ( Digital Signal Processing) and CPLD ( Complex Programmable Logic Device) is designed.

本论文通过对数据采集技术的研究，设计了一套基于DSP和CPLD技术的可编程遥测信号采集与编码系统。

This paper introduces a scheme in which a complex programmable logic device ( CPLD) is used in the three phase three pole switch high rating factor convertor to realize logic control.

介绍了在三相三开关高功率因数变换器中应用复杂可编程逻辑器件（CPLD）实现逻辑控制部分的方案。

An electronic coded lock based on in system programmable ( ISP) technology and complex programmable logic device ( CPLD) is introduced in this paper. The operation principle and design of hardware and software of electronic coded lock are introduced in detail.

介绍一种基于在系统可编程（ISP）技术和复杂可编程逻辑器件（CPLD）的新型电子密码锁的设计方法，阐述了其工作原理和软硬件设计。

The paper also suggests to use programmable logic device ( PLD) as logic control chip to control SDRAM, and so makes it possible to use SDRAM in projects, thus offers a new way to electronic design in which high speed and huge storage memory is needed.

提出了用可编程逻辑器件作为逻辑控制芯片对内存条进行控制，从而使在工程项目中使用计算机内存条成为可能，为需要大容量高速存储器的电子设计提供了一种新的思路。

Car dumper driver frequency control system constitutes a programmable logic controller, the AFE rectifier feedback device, vector inverter, drive motor, speed sensor, PC, and control cabinet.

翻车机驱动变频调速控制系统由可编程逻辑控制器、AFE整流回馈装置、矢量逆变器、驱动电动机、速度传感器、上位机以及控制柜等构成。

Based on the problem of measuring the time variable in the development of magnetostrictive liquid level sensor, a design scheme to realize the time variable measurement of high distinguishability is presented by use of complex programmable logic device ( CPLD).

针对磁致伸缩液位传感器的国产化开发研制中的时间量检测问题，提出采用复杂可编程逻辑器件（CPLD）实现高分辨力时间量检测的方案。